Innovative deep neural networks resizing for FPGA implementation in future collider experiments.

Deep Learning techniques are widely used at the LHC and have proven to be quite effective for event processing. However, the huge amount of data produced at the LHC represents a challenge, making it hard to maintain old trigger schemes and store data for offline analysis. Trigger strategies for future high-rate collider experiments invariably envisage real-time implementations of Neural Networks on FPGAs without overtaking the available resources. Herein, we propose an original method to drop unneeded input information and prune Deep Neural Networks for FPGA implementation. Our pruning strategy can select relevant input features and cut off unimportant nodes during training. The result is an overall reduction of the neural network size, with its final dimensions determined by the user. Our solution is simple to incorporate into already developed Deep Neural Network classifiers, lowering the amount of input data and network size without significant losses in performance, and allows for the individuation of the optimum network design compatible with the FPGA resources available. Promising results are presented with a road map for future advances and applications.